As semiconductor components have been become more finely structured, dynamic random access memory (DRAM) sizes have moved toward gigabits of storage capacity. In such a gigabit DRAM, components are formed to have a critical dimension of 0.18 .mu.m or less, which reduces the size of a contact hole connecting component-to-component or layer-to-layer and also reduces the alignment margin for the device.
In order to reduce the size of a contact hole formed through a photolithography process and to increase the alignment exactitude on a photo equipment, a self-aligned contact is suggested.
The self-aligned contact process may increase the alignment margin and reduce the contact resistance. Accordingly, the self-aligned contact is regarded as one of the important methods for forming a contact.
A conventional method for forming a self-aligned contact will be described below with reference to FIGS. 1, 2A, and 2B. FIG. 1 is a top plan view showing a structure of a self-aligned contact according to a conventional method. FIGS. 2A-2B are sectional views sequentially showing the process steps of a conventional method for forming a self-aligned contact, taken along a line II-II' of FIG. 1.
Referring to FIG. 2A, a device isolation layer 12, defining an active region 10b and an inactive region, is formed in a semiconductor substrate 10a. The device isolation layer 12 is formed through a conventional local oxidation of silicon (LOCOS) process or shallow trench isolation (STI) process.
After the formation of a gate oxide layer (not shown) over the semiconductor substrate 10a, a conductive layer (not shown), to be used as a gate electrode, and an insulating layer (not shown), to be used as a gate mask, are sequentially formed over the gate oxide layer. The insulating layer may, for example, be made of SiN having an etch selectivity with respect to an interlayer insulating film formed through the following process. The conductive layer may be a dual layer including a polysilicon layer and a tungsten silicide layer.
The conductive layer and the insulating layer are then patterned using a conventional photolithography process to form a gate mask 18 and gate electrodes 14 and 16. In this case a dual polysilicon layer and tungsten silicide layer are used for a conductive layer, so the resulting gate electrode 14 and 16 includes a polysilicon gate electrode portion 14 and a tungsten silicide gate electrode portion 16. For ease of disclosure, these two portions will simply be referred to as the gate electrode 14 and 16.
In order to form a lightly doped drain (LDD) structure, a low concentration source/drain impurity ion is implanted into the active region 10b at both sides of the gate electrode 14 and 16. A gate spacer 20 is then formed on both sidewalls of the gate electrode 14 and 16 and the gate mask 18. The gate spacer may be made of, for example, SiN having an etch selectivity with respect to an interlayer insulating film 22 formed through the following process. A high concentration source/drain impurity ion may be implanted into the active region 10b at both sides of the gate spacer, a transistor is completed.
The interlayer insulating film 22 is then formed over the semiconductor substrate 10a. Using a photoresist pattern (not shown) for a self-aligned contact, the interlayer insulating film 22 is then etched to form openings 24a.
Referring to FIG. 2B, after the removal of the photoresist pattern, a polysilicon layer is formed over the interlayer insulating film 22 and filling the openings 24a. The polysilicon layer is planarized down to a top surface of the interlayer insulating film 22 through an etch-back process or a chemical mechanical polishing (CMP) process, so that self-aligned contact pads 24b and 24c are formed. The contact pad 24b is electrically connected to a later-formed bit line, and the contact pad 24c is electrically connected to a later-formed capacitor lower electrode.
As the minimum design rule of a current memory cell structure is reduced, a method for forming a source/drain contact for connecting a bit line and storage node in a cell has become increasingly difficult. As shown in FIG. 2A, in the foregoing prior method, the width W of the interlayer insulating film 22 between the contact holes 24a becomes narrower in more highly-integrated components. Owing to the limitation of the photolithography technique for forming the contact holes 24a, it becomes increasingly difficult to form a photoresist pattern in highly-integrated devices.
IEDM 95, p. 907 and IEDM 96, p. 597, the disclosures of which are incorporated by reference in their entirety, disclose a self-aligned contact process.
Generally, as shown in FIG. 1, the typical shape of the self-aligned contact is of a circular or elliptical configuration. As a pattern size is reduced in this method (i.e., as a contact hole size is reduced), an area etched during an etching process is also reduced and a contact hole becomes relatively deep (i.e., high aspect ratio). As a result, a so-called "etch-stop" may be generated. In other words, the etching speed is reduced and, if severe enough, an etching byproduct, such as a polymer, cannot easily diffuse out of the deep and narrow contact hole, and the etching can stop in a severe case (using a so called "etching stop phenomenon").
In order to solve the problems, it is necessary to etch on condition of suppression of generating a polymer or to increase the etching time. However, the etch selectivity of a silicon nitride capping layer and spacer with respect to an interlayer insulating film is reduced under this condition, so that the interlayer insulating film is not selectively etched to lose the original objects of the self-aligned contact.
Based on this, Y. Kohayma et al. have suggested a new structure in which a contact hole for a a bit line pad and a lower capacitor electrode pad is united ("A Fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1 Gbit DRAM and Beyond", symp. on VLSI tech. digest of technical papers, pp. 17-18, 1997).
In this design, however, a pattern area occupied by the photoresist is so small in the foregoing circular or elliptical configuration structure that the polymer is less formed during an etching process for forming the contact hole. The polymer may alter etching speed and etch selectivity with respect to the interlayer insulating film. If the photoresist pattern area is great enough, the etch selectivity may increase.